U.S. Pat. Nos. 5,349,243 to Houghton et al. and 5,381,059 to Douglas disclose output buffers that include tristate predriver circuitry controlling the buffers' output transistors. In U.S. Pat. No. 5,311,076, Park et al. disclose a tristate data output buffer having a preset circuit, responsive to an output enable signal, for setting the buffer's output node to an intermediate voltage level in advance of a data output operation, thereby minimizing the required voltage swing at the output during a transition and thus reducing the current impulses that cause noise. None of these output buffers have any latching capability.
In conventional buffer circuits, it is very difficult to provide both transparent latching and a tristate output in the same circuit, with independent operation, while maintaining high speed. In tristate buffers, in addition to logic HIGH and LOW output voltage levels, a third high impedance state can be asserted, if desired. Such buffers generally employ logic gates in the signal path leading to the main output driver transistors, and responsive to an output enable control signal, to shut off both output transistors whenever the high impedance state is required. A transparent latch element transmits its input to its output whenever a latch enable control signal is asserted, thereby allowing the output value to change whenever the input changes, but when the control signal goes low, the latch element then stores and outputs the value that the input last had when the control signal changed, ignoring any subsequent changes at the latch's input until the control signal is reasserted. Such a latch element could be implemented, for example, by a pair of cross-coupled inverters with a pass gate provided on the latch's input side. Buffer circuits that include latches typically locate one or more of a latch's components directly in the buffer's signal path. Logic gates or latch components in the signal path tend to slow signal propagation to the buffer's output, even when the buffer is not tristated or latched. In order to maintain high speed operation, prior devices are generally either tristate output buffers with no latching capability at all, as in the aforementioned patents, or are limited to providing latching operation only when the output is tristated, i.e. in a high impedance state.
Thus, in U.S. Pat. No. 5,327,317, Lee discloses a buffer circuit serving as a data line driver for a memory. The circuit includes a helper flip-flop section connected to I/O lines from the memory array. The I/O lines are allowed to develop a differential potential prior to clocking the flip-flop with a strobing enable signal. While enabled, the flip-flop uses positive feedback to pull the true and complement output signals towards opposite supply potentials, thus amplifying the differential input signal received from the I/O lines. The large differential output potential provided by the flip-flop drives the input of a buffer section of the circuit. The buffer, in turn, drives complementary data lines. The output of the flip-flop also drives a data latch to hold the data between read operations. The latch is strobed by the same enable signal that controls the flip-flop and buffer sections, so that the latch is set or reset when one of the data lines driven by the buffer transitions low.
In U.S. Pat. Nos. 5,349,243 and 5,396,108, McClure discloses latch-controlled output drivers that include latch circuits connected to the gates of the drivers' pull-up and pull-down output transistors. In the '108 patent, the output can be tristated by disabling the pass gate inputs to the latches and by activating an enable/disable control circuit that turns both output transistors off. A third latch continues to receive input signals so that at the end of a tristate disable period, the pair of latches controlling the output transistors can be restored to the last valid input state. The latches cannot be made transparent independent of the tristate output driver stage.
An object of the present invention is to provide a high speed buffer circuit with independent tristate and transparent latch capabilities.